systemverilogforlearning

 SystemVerilog supports the usage of Soft Constraints to specify a default value e.g      class  base;            rand    bit [3:0]   r;              constraint cb  {  soft r inside  { [0:3] };}          endclass If there is a conflict between multiple soft constraints, who wins ?  e.g     class   base;                   rand bit [3:0]  r;                       constraint   low { soft r == 0; }                       constraint  high  { soft  r > 10; }            endclass ** Here later constraints are higher priority than the earlier, so  r> 10 wins e.g   class  stuff;            rand  base    b_h ;            constraint  higher  { soft  b_h.r == 9; } endclass ** Here, b_h.r == 9  wins over the rest of the above e.g   class  base_extend  extends  base;           constraint hi { soft r == 2; } endclass ** Here, the extend class has higher priority on the variable r

 In SystemVerilog Constraints can be enabled/disabled to allow the tests without the constraint using the keyword  "constraint_mode"   e.g           class Transcation;                   rand    logic [15:0] addr;                  constraint align { addr[1:0] == 2'b0;}            endclass module test;        Transcation   t_h  ;    // create a handle        initial  begin           t_h   =  new();   // generate a handle by allocating memory           t_h.align. constraint_mode(0) ;    // disable the constraint by making it "0"           t_h.align. constraint_mode(1) ;    // enable the constraint by making it "1"       end endmodule           

  How can we generate a non-repeating a random set of values ? SystemVerilog introduces keyword by name "randc" The "randc" modifier creates a cyclic random variable in a class e.g       typedef   enum bit [3:0] { SPADE, CLUB, ....., QUEEN, HEART} cards_t;       class gambler;                       randc  cards_t                    cards ;  // cyclic randomization of cards                       rand     bit [2:0]                   dice   ;  // uniform randomzation of dice                       constraint dice_vals { dice  inside {[1:6]};}        endclass

 Implication Constraints in SystemVerilog Creates dependency between two expressions. This introduces a concept that if  a is "TRUE" then  b will be "TRUE" e.g typedef   enum   [LONG, SHORT]  packet_size; class  packet;         rand  packet_size       packet_size_t;         rand bit [7:0] addr;         constraint packet_c { (packet_size_t  == LONG  -> (addr == 200);}  endclass    

 In SystemVerilog how do we define constraint to have values a higher probability than others? For this we use an Weighted Distribution concept using "dist"   syntax For e.g    class Transcation;                  rand bit [1:0]     src_addr, dst_addr;                  constraint  c_distribution  {                              src_addr    dist   { 5 := 2, [7:9] := 3};                              dst_addr  dist     { 5: /2 ,  [7:9] : /3};                    }     endclass The above two expression  '5:=2'  and '5:/2' are equivalent [7:9] := 3 says to make the weight for each value in the range equal to 3 [7:9] :/3  says to divide the weight across each value in the range

  SystemVerilog defines a way to pick inputs randomly from a list of values The   "inside"  operator can hold a list of values, ranges and even arrays For e.g         class choices;                 rand   bit [3:0]   m,p,q,r;                 constraint c_p   { p inside    { 1, [3:6]};          end class

In SystemVerilog, we need to specify the keyword "rand" or "randc" to generate class variables randomly. Below, we can see an small example defined class  game;           rand      bit [2:0]  dice;   // using randomization we can have 8-possible values                       bit [9:0]  money;  // This variable is not random            // Apply in-line constraints to generate dice values within a particular range           constraint   dice_values { dice  inside {[1:5]}; }    endclass //*** To generate the above class variables use randomize() method .  module top;          game      game_h;     // class game handle defined          initial begin                   game_h     = new();  // generate the class game by allocating memory                   repeat(50)                           if (! game_h.randomize() )                              $fatal (1, "Game::randomize() failed");                              $display("Rolled a %0d", game_h.dice);

  Let's take an example of verification of an 32-bit adder.  Can we complete the exhaustive verification of 32-bit adder without generating  the inputs randomly? If so, how much duration (years) it takes to complete the same.  Looking at the above scenario and TTM (Time To Market), we need to emphasize  on Randomization of the inputs. SystemVerilog has a powerful in built randomization generator which helps in  reaching the stimuli to most of the input region space. This not only helps in generating values in random fashion but also helps in  detecting the corner case scenarios (issues) which were unnoticed until now.

Ususally our Test bench works with a basic set of classes.  The basic question is how do we add new functionality to the existing class definition.  SystemVerilog comes out with an concept of extending a class to add new behavior which introduces to new class definition. For  e.g                        Class Transcation;                                bit[31:0]    src_addr,  dst_addr,  crc, data[8];                                 function void  calc_crc();                                       crc  = src_addr  ^  dst_addr  ^  data.xor();                                  endfunction                         endclass Now, how do we add new functionality? Extend the existing class into a new one Override existing methods, add new methods & properties              Class  Bad_Tr   extends Transcation;                         bit   bad_crc;                         function void calc_crc();                                 super.calc_crc();        // This refers to the parent Class to inhe

SystemVerilog Supports the concept of definining External Methods which are used extensively. The below description points out how this can be beneficial. This is mainly used to move the method details outside of the class body to remove hinderness The class contains an "extern" definition (an prototype) of the method The implementation (body) of the method is defined outside of the class The argument names, types, qualifiers, mode and defaults must match exactly e.g              class Animal;                      int                age;                      string           name;                     extern funtion new(int age, string name);                     extern function  void print();               endclass     ****  Now accessing these function definition from outside and update the same               function  Animal :: new (int age, string name);                       // define the requirements               endfuntion                          function Animal :: pr

SystemVerilog allows us to have a Shallow copy for a particular object A New object can be constructed that is a copy of the values/properties of an existing object For e.g               class    animal;                          int       age;                          string  name;               endclass               module test;                             animal  a_h, b_h;            // Two separate handles                             initial     begin                                        a_h           = new (10, "Tiger");  // construct an animal object                                        b_h           = new a_h;                // construct b_h and copy the values from a_h                                        b_h.age    = 6;                                         $display (a_h.age, b_h.age);     // a_h & b_h refer to two separte objects                              end                 endmodule           

During the building up of  SystemVerilog Environment sometimes we end in facing NULL Pointer error. Question is how do we identify the issue ? Let us look at one small example and analyze. e.g                  module test;                         class       animal;                                int   age;                         endclass                          animal      a_h;      //  class handle pointer                          initial   begin                                     a_h.age  =  52;                                     a_h         = new();                           end                       endmodule ****      Here we forgot to call the new() for class animal handle (a_h)              before accessing its objects.  ****      Since the Class handle was not created it created NULL Handle issue. *****    By reversing the handle creation and assignment, we can get ride of             NULL pointer issue.                            

Here, i am illustrating an example where one of the class  is defined as an object inside another class and created during the generation       class  mouth;             int     teeth;             function  new (int teeth);                   this.teeth   =  teeth;             endfunction        endclass        class  animal;               int     age;               mouth  m_h;           // handle defined for the class mouth but not yet created               function new (int age, teeth);                     this.age     =  age;                     m_h          = new(teeth);               endfunction         endclass         module top;                 animal     a_h;                 initial begin                           a_h    =  new (1, 4);                  end          endmodule                         

In SystemVerilog a handle variable holds an reference to an object In the below example handle is defined but not constructed              animal     a_h ;    // Here handle is defined but the objects are null              a_h      =  new() ;   // Here the Handle is created using new()   once the handle is created, internally it will create the objects  by alloting new memory locations

System verilog has a default reference pointer to its own objects.  we use the  "this"  syntax to refer to its own objects within the methods e.g          class animal;                  int        age;                  string   name;                     function new (int age, string name);                           this.age        =  age;                           this.name     =  name;                  endfunction            endclass           module top;                    animal    a_h;                   initial begin                         a_h    = new(7, "lion");                    end            endmodule      

Every Class constructor has an implicit  new()  method When called, allocates memory to hold the properites Properties are set to the uninitialized value i.e  X for 4-state , 0 for 2-state and " " for string for ex:          class animal;               int        age;               string   name;                function new();                         age        = 1;                          name    = "Friend";                endfunction             endclass module top();            animal   a_h;    // declare the class handle            initial begin                  a_h         =  new();                  $display("%0d  '%s' ", a_h.age, a_h.name);            end endmodule             

An class object properities are accessed with the handle and dot operator(.) e.g      module top();                    class animal;                  int      age;                  string name;              endclass             animal   a_h ;       // create handle to animal object             initial begin                   a_h             = new();                   a_h.name        = "Tiger";                   a_h.age         = 10;            end endmodule

In System Verilog the Data abstract are defined using the  class definition .  To get an overview of the class , here are some points which can be considered Class is a user-defined data type class defines data, functions/tasks to perform some operation on the data defined System Verilog classes support a subset of object-oriented features Abstract data modeling Inheritance Example of class definition    class my_class;                logic[2:0]  address;                logic[7:0]  data;                bit            parity;            //***** Declaration of user-defined methods ( task/function)               function calc_parity();                         ------ enter your code here              endfunction     endclass: my_class

System Verilog   is an  IEEE std 1800-2005  Hardware Design and Verification Language. System Verilog  makes it more practical to write an readable and reusable code. From the Design Verification engineer point of view, System Verilog Provides constructs  which can be used to create transaction using randomization approach by applying constraints. System Verilog also gives construct to add assertion and Functional Coverage methodologies