How to define Constraint Set Memership in SystemVerilog

 SystemVerilog defines a way to pick inputs randomly from a list of values

  • The   "inside"  operator can hold a list of values, ranges and even arrays
For e.g

        class choices;
                rand   bit [3:0]   m,p,q,r;

                constraint c_p   { p inside   { 1, [3:6]};
         end class

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