Need for Randomization in SystemVerilog

 Let's take an example of verification of an 32-bit adder. 

Can we complete the exhaustive verification of 32-bit adder without generating 

the inputs randomly?

If so, how much duration (years) it takes to complete the same. 

Looking at the above scenario and TTM (Time To Market), we need to emphasize

 on Randomization of the inputs.

SystemVerilog has a powerful in built randomization generator which helps in 

reaching the stimuli to most of the input region space.

This not only helps in generating values in random fashion but also helps in 

detecting the corner case scenarios (issues) which were unnoticed until now.



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