How do we define the basic class

In System Verilog the Data abstract are defined using the class definition. 

To get an overview of the class , here are some points which can be considered

  • Class is a user-defined data type
  • class defines data, functions/tasks to perform some operation on the data defined
  • System Verilog classes support a subset of object-oriented features
    • Abstract data modeling
    • Inheritance

Example of class definition

  class my_class;

               logic[2:0]  address;
               logic[7:0]  data;
               bit            parity;

           //***** Declaration of user-defined methods ( task/function)

            function calc_parity();

                    ------ enter your code here

             endfunction

   endclass: my_class

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