What is Class based Randomization and how do we define ?

In SystemVerilog, we need to specify the keyword "rand" or "randc" to generate class variables randomly.

Below, we can see an small example defined

class  game;
          rand     bit [2:0]  dice;   // using randomization we can have 8-possible values
                      bit [9:0]  money;  // This variable is not random 

          // Apply in-line constraints to generate dice values within a particular range
          constraint   dice_values { dice  inside {[1:5]}; }   
endclass

//*** To generate the above class variables use randomize() method.

 module top;

         game      game_h;     // class game handle defined

         initial begin
                  game_h     = new();  // generate the class game by allocating memory
                  repeat(50) 
                         if (!game_h.randomize())
                             $fatal (1, "Game::randomize() failed");
                             $display("Rolled a %0d", game_h.dice);
                  end
 endmodule
  

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