How to define a Cyclic Randomization in SystemVerilog

 How can we generate a non-repeating a random set of values ?

  • SystemVerilog introduces keyword by name "randc"
  • The "randc" modifier creates a cyclic random variable in a class
e.g
      typedef   enum bit [3:0] { SPADE, CLUB, ....., QUEEN, HEART} cards_t;

      class gambler;
                      randc  cards_t                    cards ;  // cyclic randomization of cards
                      rand     bit [2:0]                   dice   ;  // uniform randomzation of dice
                      constraint dice_vals { dice  inside {[1:6]};}
       endclass

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