How do we identity NULL Handles?

During the building up of  SystemVerilog Environment sometimes we end in facing NULL Pointer error.

Question is how do we identify the issue ?

Let us look at one small example and analyze.

e.g

                 module test;
                        class       animal;
                               int   age;
                        endclass
                         animal      a_h;      //  class handle pointer
                         initial   begin
                                    a_h.age  =  52;
                                    a_h         = new();
                          end
                      endmodule

****      Here we forgot to call the new() for class animal handle (a_h) 
            before accessing its objects. 
****      Since the Class handle was not created it created NULL Handle issue.
*****    By reversing the handle creation and assignment, we can get ride of 
           NULL pointer issue.
                           

Comments

Post a Comment

Popular posts from this blog

What is Class based Randomization and how do we define ?

In SystemVerilog, we need to specify the keyword "rand" or "randc" to generate class variables randomly. Below, we can see an small example defined class  game;           rand      bit [2:0]  dice;   // using randomization we can have 8-possible values                       bit [9:0]  money;  // This variable is not random            // Apply in-line constraints to generate dice values within a particular range           constraint   dice_values { dice  inside {[1:5]}; }    endclass //*** To generate the above class variables use randomize() method .  module top;          game      game_h;     // class game handle defined          initial begin                 ...
Read more

How Disable Constraints in SystemVerilog

 In SystemVerilog Constraints can be enabled/disabled to allow the tests without the constraint using the keyword  "constraint_mode"   e.g           class Transcation;                   rand    logic [15:0] addr;                  constraint align { addr[1:0] == 2'b0;}            endclass module test;        Transcation   t_h  ;    // create a handle        initial  begin           t_h   =  new();   // generate a handle by allocating memory           t_h.align. constraint_mode(0) ;    // disable the constraint by making it "0"           t_h.align. constraint_mode(1) ;    // enable the constraint by making it "1"       e...
Read more

How do we define Weighted Distribution Constraint in SystemVerilog

 In SystemVerilog how do we define constraint to have values a higher probability than others? For this we use an Weighted Distribution concept using "dist"   syntax For e.g    class Transcation;                  rand bit [1:0]     src_addr, dst_addr;                  constraint  c_distribution  {                              src_addr    dist   { 5 := 2, [7:9] := 3};                              dst_addr  dist     { 5: /2 ,  [7:9] : /3};                    }     endclass The above two expression  '5:=2'  and '5:/2' are equivalent [7:9] := 3 says to make the weight for each value in the range equal ...
Read more