Usage of Soft Constraints in SystemVerilog

 SystemVerilog supports the usage of Soft Constraints to specify a default value

e.g

     class  base;

           rand    bit [3:0]   r;

             constraint cb  {  soft r inside  { [0:3] };} 

        endclass

If there is a conflict between multiple soft constraints, who wins ? 

e.g    class   base;

                  rand bit [3:0]  r;

                      constraint   low { soft r == 0; }

                      constraint  high  { soft  r > 10; }

           endclass

** Here later constraints are higher priority than the earlier, so  r> 10 wins

e.g 

class  stuff;

           rand  base    b_h ;

           constraint  higher  { soft  b_h.r == 9; }

endclass

** Here, b_h.r == 9  wins over the rest of the above

e.g 

class  base_extend  extends  base;

          constraint hi { soft r == 2; }

endclass


** Here, the extend class has higher priority on the variable r


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