How Disable Constraints in SystemVerilog

 In SystemVerilog Constraints can be enabled/disabled to allow the tests without the constraint using the keyword  "constraint_mode" 

e.g

          class Transcation;

                  rand    logic [15:0] addr;

                 constraint align { addr[1:0] == 2'b0;}

           endclass

module test;

       Transcation   t_h  ;    // create a handle

       initial  begin

          t_h   =  new();   // generate a handle by allocating memory

          t_h.align.constraint_mode(0);    // disable the constraint by making it "0"

          t_h.align.constraint_mode(1);    // enable the constraint by making it "1"

      end

endmodule

          


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