How to define an implication Constraints in SystemVerilog

 Implication Constraints in SystemVerilog Creates dependency between two expressions.

This introduces a concept that if  a is "TRUE" then  b will be "TRUE"

e.g

typedef   enum   [LONG, SHORT]  packet_size;

class  packet;

        rand  packet_size       packet_size_t;

        rand bit [7:0] addr;

        constraint packet_c { (packet_size_t  == LONG  -> (addr == 200);}

 endclass 

  



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