Learn about class extension

Ususally our Test bench works with a basic set of classes. 
The basic question is how do we add new functionality to the existing class definition. 

SystemVerilog comes out with an concept of extending a class to add new behavior which introduces to new class definition.

For  e.g 
                      Class Transcation;
                               bit[31:0]    src_addr,  dst_addr,  crc, data[8];

                                function void  calc_crc();
                                      crc  = src_addr  ^  dst_addr  ^  data.xor();
                                 endfunction
                        endclass

Now, how do we add new functionality?
  • Extend the existing class into a new one
  • Override existing methods, add new methods & properties
             Class  Bad_Tr   extends Transcation;
                        bit   bad_crc;
                        function void calc_crc();
                                super.calc_crc();        // This refers to the parent Class to inherit the calc_crc()
                                if (bad_crc)                // Add new logic to the extended class
                                   crc  = ~ crc;
                         endfunction
               endclass
                    

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