systemverilogforlearning

 In SystemVerilog Constraints can be enabled/disabled to allow the tests without the constraint using the keyword  "constraint_mode"   e.g           class Transcation;                   rand    logic [15:0] addr;                  constraint align { addr[1:0] == 2'b0;}            endclass module test;        Transcation   t_h  ;    // create a handle        initial  begin           t_h   =  new();   // generate a handle by allocating memory           t_h.align. constraint_mode(0) ;    // disable the constraint by making it "0"           t_h.align. constraint_mode(1) ;    // enable the constraint by making it "1"       e...

  How can we generate a non-repeating a random set of values ? SystemVerilog introduces keyword by name "randc" The "randc" modifier creates a cyclic random variable in a class e.g       typedef   enum bit [3:0] { SPADE, CLUB, ....., QUEEN, HEART} cards_t;       class gambler;                       randc  cards_t                    cards ;  // cyclic randomization of cards                       rand     bit [2:0]                   dice   ;  // uniform randomzation of dice                       constraint dice_vals { dice  inside {[1:6]};}        endclass

 Implication Constraints in SystemVerilog Creates dependency between two expressions. This introduces a concept that if  a is "TRUE" then  b will be "TRUE" e.g typedef   enum   [LONG, SHORT]  packet_size; class  packet;         rand  packet_size       packet_size_t;         rand bit [7:0] addr;         constraint packet_c { (packet_size_t  == LONG  -> (addr == 200);}  endclass    

 In SystemVerilog how do we define constraint to have values a higher probability than others? For this we use an Weighted Distribution concept using "dist"   syntax For e.g    class Transcation;                  rand bit [1:0]     src_addr, dst_addr;                  constraint  c_distribution  {                              src_addr    dist   { 5 := 2, [7:9] := 3};                              dst_addr  dist     { 5: /2 ,  [7:9] : /3};                    }     endclass The above two expression  '5:=2'  and '5:/2' are equivalent [7:9] := 3 says to make the weight for each value in the range equal ...

  SystemVerilog defines a way to pick inputs randomly from a list of values The   "inside"  operator can hold a list of values, ranges and even arrays For e.g         class choices;                 rand   bit [3:0]   m,p,q,r;                 constraint c_p   { p inside    { 1, [3:6]};          end class

In SystemVerilog, we need to specify the keyword "rand" or "randc" to generate class variables randomly. Below, we can see an small example defined class  game;           rand      bit [2:0]  dice;   // using randomization we can have 8-possible values                       bit [9:0]  money;  // This variable is not random            // Apply in-line constraints to generate dice values within a particular range           constraint   dice_values { dice  inside {[1:5]}; }    endclass //*** To generate the above class variables use randomize() method .  module top;          game      game_h;     // class game handle defined          initial begin                 ...